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ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI341ART
3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity
Features
* Supply voltage, VCC = 3.3V 5% * Each Port is compatible w/ DVI, HDMI 1.1, HDMI 1.2 or HDMI 1.3 signals * Supports both AC-coupled and DC-coupled inputs * Support for 8-bit, 10-bit, and 12-bit deep color per channel * High Performance, up to 2.5 Gbps per channel * Switching support for 3 side band signals (SCL, SDA and HPD) * 5V Tolerance on all side band signals * SCL, SDA, and HPD pins are the only pins that can support HOT INSERTION * Integrated 50-ohm (10%) termination resistors at each high speed signal input * Configurable output swing control (500mV, 750mV, 1000mV) * Configurable Pre-Emphasis levels (0dB, 1.5dB, 3.5dB, & 6.0dB) * Configurable De-Emphasis (0dB, -3.5dB, -6.0dB, -9.5dB) * Optimized Equalization Single default setting will support all cable lengths * ESD protection = 8kV (typical) on high-speed data channels only * Propagation delay 2ns * High Impedance Outputs when disabled * Packaging (Pb-free & Green): 80-contact LQFP (FF80)
Description
Pericom Semiconductor's PI3HDMI341ART 3:1 active switch circuit is targeted for high-resolution video networks that are based on DVI/HDMI standards and TMDS signal processing. The PI3HDMI341ART is an active 3 TMDS to 1 TMDS receiver switch with Hi-Z outputs. The device receives differential signals from selected video components and drives the video display unit. It provides three controllable output swings that can be controlled through a single bit. The allowable output swings are 500mV, 750mV and 1000mV. This solution also provides a unique advanced pre-emphasis technique to increase rise and fall times which are reduced during transmission across long distances. Each complete HDMI/DVI channel also has slower speed, side band signals, that are required to be switched. Pericom's solution provides a complete solution by integrating the side band switch together with the high speed switch in a single solution. Using Equalization at the input of each of the high speed channels, Pericom can successfully eliminate deterministic jitter caused by long cables from the source to the sink. The elimination of the deterministic jitter allows the user to use much longer cables (up to 25 meters). The maximum DVI/HDMI Bandwidth of 2.5 Gbps provides 12bit deep color support, which is offered by HDMI revision 1.3. Due to its active uni-directional feature, this switch is designed for usage only for the video receiver's side. For consumer video networks, the device sits at the receiver's side to switch between multiple video components, such as PC, DVD, STB, D-VHS, etc. The PI3HDMI341ART is the industry's first active DVI/ HDMI switch compatible with HDMI 1.1, 1.2, and 1.3 which ensures transmitting high-bandwidth video streams from video components to the display unit. The PI3HDMI341ART also provides enhanced robust ESD/EOS protection of 8kV, which is required by many consumer video networks today. The Optimized Equalization provides the user a single optimal setting that can provide HDMI compliance for all cable lengths: 1meter to 20meters and color depths of 8bit/ch, or 12bit/ch. Pericom also offers the abiility to fine tune the equalization settings in situations where cable length is known. For example, if 25meter cable length is required, Pericom's solution can be adjusted to 16dB EQ to accept 25metere cable length.
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PS8883
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ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity
Pin Configuration
EQ_S1 GND A34 B34 VCC A33 B33 GND A32 B32 VCC A31 B31 GND SCL3 SDA3 HPD3 VCC OE EQ_S0 VCC HPD2 SDA2 SCL2 GND GND B21 A21 VCC B22 A22 GND B23 A23 VCC B24 A24 GND VCC HPD1
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16 17
18
19
20
22 21
HPD_SINK SDA_SINK SCL_SINK GND GND Z1 Y1 VCC Z2 Y2 GND Z3 Y3 VCC Z4 Y4 GND S3 S2 S1
OC_S2 OC_S0 OC_S1 VCC GND A14 B14 VCC A13 B13 GND A12 B12 VCC A11 B11 GND SCL1 SDA1 OC_S3
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PS8883 01/05/07
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity
Pin Description
Pin # 6,9,12,15 68, 71, 74, 77 49, 52, 55, 58 5, 8, 11, 14 67, 70, 73, 76 48, 51, 54, 57 4, 10, 16 24, 30, 36, 37, 47, 53, 59, 65, 66, 72, 78 80 62 44 40 Pin Name A11, A12, A13, A14 A21, A22, A23, A24 A31, A32, A33, A34 B11, B12, B13, B14 B21, B22, B23, B24 B31, B32, B33, B34 GND HPD1 HPD2 HPD3 HPD_Sink O O O I I/O I I I I I I Description Port 1 TMDS Positive inputs Port 2 TMDS Positive inputs Port 3 TMDS Positive inputs Port 1 TMDS Negative inputs Port 2 TMDS Negative inputs Port 3 TMDS Negative inputs Ground Port 1 HPD output Port 2 HPD output Port 3 HPD output Sink side hot plug detector input. High: 5-V power signal asserted from source to sink and EDID is ready. Low: No 5-V power signal asserted from source to sink, or EDID is not ready. Output Enable, Active LOW Port 1 DDC Clock Port 2 DDC Clock Port 3 DDC Clock Sink Side DDC Data Port 1 DDC Data Port 2 DDC Data Port 3 DDC Data Sink Side DDC Data Source Input Selector 3.3V Power Supply O O I I TMDS positive outputs TMDS negative outputs Equalizer controls(1) Output buffer controls Note: OC_S3 has an internal pull-up resistor. OC_S2 has an internal pull-down resistor.
42 3 64 46 38 2 63 45 39 21,22,23 7, 13, 17 27, 33, 43, 50, 56 61, 69, 75, 79 34, 31, 28, 25 35, 32, 29, 26 41, 60 19, 18, 20, 1
OE SCL1 SCL2 SCL3 SCL_Sink SDA1 SDA2 SDA3 SDA_Sink S1, S2, S3 VCC Y1, Y2, Y3, Y4 Z1, Z2, Z3, Z4 EQ_S0, EQ_S1 OC_S0, OC_S1, OC_S2, OC_S3
I I/O I/O I/O I/O I/O I/O I/O I/O I
Note: 1. EQ_S0 has an internal pull-down and EQ_S1 has an internal pull-up
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ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity
Switch Block Diagram

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01/05/07
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity
Truth Table
Control Pins S1 H L L L S2 x H L L S3 x x H L Y/Z A1/B1 A2/B2 A3/B3 None (Hi-Z) I/O Selected SCL_Sink SDA_Sink SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 None (Hi-Z) HPD1 HPD_Sink L L L Hot Plug Detect Status HPD2 L HPD_Sink L L HPD3 L L HPD_Sink L
OC Setting Value Logic Table
Input Control Pins OC_S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OC_S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OC_S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 OC_S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vswing (mV) 500 750 1000 500 500 500 500 500 500 340 270 160 1000 830 500 330 Setting Value Vos (V) 3.06 2.95 2.84 3.02 3.06 3.05 2.97 2.9 3.08 3.08 3.08 3.08 2.85 2.85 2.85 2.85 Pre-emphasis/De-emphasis (dB) none none none none 0 1.5 3.5 6 0 -3.5 -6 -9.5 0 -3.5 -6 -9.5
EQ Setting Value Logic Table
EQ_S1 0 0 1 1 EQ_S0 0 1 0 1 Setting Value 3dB on all high speed inputs 8dB on all high speed inputs Optimized Equalization enabled on all high speed inputs (default value if both EQ_S0 and EQ_S1 are left floating) 16dB on all high speed inputs
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ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................................... -65C to +150C Supply Voltage to Ground Potential................................-0.5V to +4.0V DC Input Voltage ...............................................................-0.5V to VCC DC Output Current....................................................................... 120mA Power Dissipation ........................................................................... 1.0W
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended Operating Conditions
Symbol VCC TA VID VIC VCC RT Parameter Supply Voltage Operating free-air temperature Receiver peak-to-peak differential input voltage Input common mode voltage TMDS output termination voltage Termination resistance Signaling rate Control Pins (OC_Sx, EQ_Sx, S, OE) VIH VIL VI(DDC) VIH VIL LVTTL High-level input voltage LVTTL Low-level input voltage Input voltage LVTTL High-level input voltage LVTTL Low-level input voltage 2 GND GND 2 GND VCC 0.8 5.5 5.3 0.8 V Min. 3.135 0 150 2 3.135 45 0 3.3 50 Typ. 3.3 Max. 3.465 70 1560 VCC + 0.01 3.465 55 2.5 Units V C mVp-p V V ohm Gbps
TMDS Differential Pins (A/B)
DDC Pins (SCL, SCL_SINK, SDA, SDA_SINK) V Status Pins (HPD_SINK) V
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01/05/07
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity
TMDS Compliance Test Results
Item Operating Conditions Termination Supply Voltage, VCC Terminal Resistance Source DC Characteristics at TP1 Single-ended high level output voltage, VH Single-ended low level output voltage, VL Single-ended output swing voltage, Vswing Single-ended standby (off) output voltage, Voff Transmitter AC Characteristics at TP1 Risetime/Falltime (20%-80%) Intra-Pair Skew at Transmitter Connector, max Inter-Pair Skew at Transmitter Connector, max Clock Jitter, max Sink Operating DC Characteristics at TP2 Input Differential Voltage Level, Vdiff Input Common Mode Voltage Level, VICM 150 Vdiff 1200mV ( VCC - 300mV) Vicm ( VCC37.5mV) Or VCC 10% 150mV VDIFF 1200mV ( VCC - 300mV) Vicm ( VCC37.5mV) Or VCC 10% 75ps Risetime/Falltime 0.4 Tbit (75ps tr/tf 242ps) @ 1.65 Gbps 0.15 Tbit (90.9ps @ 1.65 Gbps) 0.2 Tpixel (1.2ns @ 1.65 Gbps) 0.25 Tbit (151.5ps @ 1.65 Gbps) 240ps 60ps max 100ps max 82ps max VCC 10mV ( VCC - 600mV) VL ( VCC- 400mV) 400mV Vswing 600mV VCC 10mV VCC 10mV ( VCC - 600mV) VL ( VCC 400mV) 400mV Vswing 600mV VCC 10mV 3.3V 5% 50-ohm 10% 3.30 5% 45 to 55-ohm HDMI 1.3 Spec Pericom Product Spec
Sink DC Characteristics When Source Disabled or Disconnected at TP2 Differential Voltage Level VCC 10mV VCC 10mV
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PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity
Electrical Characteristics (over recommended operating conditions unless otherwise noted)
Symbol ICC PD Parameter Supply Current Power Dissipation Test Conditions VIH = VCC, VIL = VCC - 0.4V, RT = 50-ohm, VCC = 3.3V Am/Bm = 1.65 Gbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 165 MHz clock VCC10 VCC - 600 VCC = 3.3V, RT = 50-ohm Pre-emphasis/De-emphasis = 0dB 400 Min.
Typ.(1) 190 394
Max. 230 657
Units mA mW
TMDS Differential Pins (A/B; Y/Z) VOH VOL Vswing VOD(O) VOD(U) VOC(SS) |I(OS)| Single-ended high-level output voltage Single-ended low-level output voltage Single-ended output swing voltage Overshoot of output differential voltage Undershoot of output differential voltage Change in steady-state common-mode output voltage between logic states Short circuit output current OC_S0 = VCC, Am/Bm = 250 Mbps HDMI data pattern, m = 2, Peak-to-peak output differential voltage 3, 4 A1/B1 = 25 MHz clock Single-ended input voltage under high impedance input or open input Input termination resistance II = 10A VIN = 2.9V VI = 0.1VCC to 0.9VCC to isolated DDC ports VI = 0V IO = 3mA, VO = 0.4V VI = 3.3V, II = 100A IOH = -8mA IOH = 8mA 1.5(2) 2.4 0.4 560 800 VCC - 10 45 50 VCC + 10 VCC - 400 600 6% 12% 0.5 15% 25% 5 12 840 1200 VCC + 10 55 mVp-p 2x Vswing mV mA mV
VODE(SS) Steady state output differential voltage VODE(PP) VI(open) RINT
mV ohm
DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK) |Ilkg| CIO RON VPASS Input leakage current Input/output capacitance Switch resistance Switch output voltage 0.1 7.5 25 2.0 50 2.5(3) 2 A pF ohm V V V
Status Pins (HPD) VOH(TTL) TTL High-level output voltage VOL(TTL) TTL Low-level output voltage
(Table Continued)
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PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity
Electrical Characteristics (Continued)
Symbol |IIH| |IIL| Parameter High-level digital input current Low-level digital input current Test Conditions VIH= 2.0V or VCC VIL = GND or 0.8V VIH = 5.3V VIH = 2.0V or VCC VIL = GND or 0.8V Min. Typ.(1) 0.1 0.1 23 0.1 0.1 Max. 2 2 100 2 2 A Units Control Pins (OC_Sx, EQ_Sx, S, OE) A
Status Pins (HPD_SINK) |IIH| |IIL| High-level digital input current Low-level digital input current
Notes: 1. All typical values are at 25C and with a 3.3V supply. 2. The value is tested in full temperature range at 3.0V. 3. The value is tested in full temperature range at 3.6V.
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ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity
Switching Characteristics (over recommended operating conditions unless otherwise noted)
Symbol tpd tr tf tsk(p) tsk(D) tsk(o) tjit(pp) tjit(pp) tDE tSX ten tdis Parameter Propagation delay Differential output signal rise time (20% - 80%) Differential output signal fall time (20% - 80%) Pulse skew Intra-pair differential skew Inter-pair differential skew(2) pre-emphasis/de-emphasis = 0dB, Am/Bm = 1.65 Gbps HDMI data pattern, m = 2 ,3, 4 A1/B1 = 165 MHz clock de-emphasis = -3.5dB, Am/Bm = 250 Mbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 25 MHz clock Peak-to-peak output jitter from Y/Z(1) residual jitter Peak-to-peak output jitter from Y/Z(2:4) residual jitter De-emphasis duration Select to switch output Enable time Disable time Propagation delay from SCLn to SCL_SINK or SDAn to SDA_SINK or SDA_SINK to SDAn Propagation delay (from HPD_SINK to the active port of HPD) Switch time (from port select to the latest valid status of HPD) 75 VCC = 3.3V, RT = 50-ohm, pre-emphasis/de-emphasis = 0dB 75 Test Conditions Min. TMDS Differential Pins (Y/Z)
Typ.(1) 2000
Max.
Units
240 240 7 23 15 18 240 6 6 6 10 10 10 ns 50 50 100 30 50 ps
DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK) tpd(DDC) CL = 10pF 0.4 2.5 ns
Control and Status Pins (OC_SX, EQ_SX, S, HPD_SINK, HPD) tpd(HPD) tsx(HPD) 2 CL = 10pF 3 6.0 ns 6.5
Notes: 1. All typical values are at 25C and with a 3.3V supply. 2. tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of a device when inputs are tied together.
Application Information
Supply Voltage All VCC pins are recommended to have a 0.01uF capacitor tied from VCC to GND to filter supply noise TMDS inputs Standard TMDS terminations have already been integrated into Pericom's PI3HDMI341ART device. Therefore, external terminations are not required. Any unused port must be left floating and not tied to GND.
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PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity
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DATE: 07/27/06
Notes: 1) All dimensions are in millimeters, angles in degrees 2) Ref JEDEC: MS-026/BDD 3) Package outline exclusive of mold flash and metal burr
DESCRIPTION: 80-pin, Low Profile Quad Flat Package (LQFP)
PACKAGE CODE: FF80 DOCUMENT CONTROL #: PD-2064 REVISION: -
Ordering Information
Ordering Code PI3HDMI341ARTFFE Package Code FF Package Description 80-pin, Pb-free & Green LQFP
Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
* E = Pb-free and Green * Adding an X Suffix = Tape/Reel
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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